1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, to a semiconductor memory device incorporating a DRAM (dynamic random access memory”) array and an operating method thereof.
2. Description of the Related Art
There are two types of semiconductor memories: a non-volatile memory such as a flash memory, and a volatile memory, such as a DRAM. For both types of the semiconductor memories, one of most important problems is improvement in data hold characteristics (that is, data retention reliability). Factors affecting on data hold characteristics depend on the type of memory.
One issue for the flash memory is deterioration of the tunnel oxide film caused by repeated data write operations; the degradation of a tunnel oxide film makes it difficult to hold electrons and holes injected into the floating gate. The deterioration of the data hold characteristics in the flash memory is generally caused by the degradation of the tunnel oxide film, and therefore, the deterioration of the data hold characteristics is an “irreversible change”. One approach of maintaining the data hold characteristics is to replace degraded cells with redundant cells. Another known approach is use of an external ECC (error correction code) circuit. For example, Japanese Laid-Open Patent application No. JP-A 2002-91831 discloses a flash memory using a software ECC for specific ones of storage areas. This allows virtually avoiding the deterioration of the data hold characteristics when tunnel oxide films are degraded. In other words, the allowed number of times of rewriting data into the specific storage areas, to which the ECC is applied, is increased compared with the remaining storage areas.
As for the DRAM, on the other hand, data corruption is mainly caused by leakage of electric charges from cell capacitors, since cell data are stored as electric charges by the cell capacitors. To avoid the data corruption, data refreshing is repeatedly performed at certain time intervals in the DRAM. The data refreshing allows the cell capacitors to be recharged with electric charges.
As thus described, data hold characteristics of the DRAM, which depend on the quantity of electric charges accumulated in the cell capacitors, are not irreversibly deteriorated. One approach for improving the data hold characteristics is to increase accumulated electric charges, for example, by increasing the capacitance of the cell capacitors. Japanese Laid Open Patent Application No. JP-A Heisei 8-212772 discloses such DRAM in which the pitches of word lines and bit lines in a highly reliable area requiring high reliability are larger than those in other areas. This allows increasing the capacitance of cell capacitors in the highly reliable area, and thereby increasing the electric charges accumulated in the cell capacitors.
Nevertheless, the DRAM disclosed in this Laid Open Patent Application undesirably increases the complexity of the manufacture process, according to the investigation of the inventor of the present invention. In the disclosed DRAM, in which the pitches of word lines and bit lines in the highly reliable area are larger than those in other areas, the shape of the memory cells is different between the highly reliable area and the other areas. Integrating differently-shaped memory cells within a single chip undesirably decreases the manufacture process uniformity over the chip, and therefore increases the complexity of the manufacture process.